There are two major categories of computer memory: non-volatile memory and volatile memory. Non-volatile memory does not require constant input of energy in order to retain information whereas volatile memory does. In non-volatile memory devices, the memory state can be retained for days to decades without power consumption. Examples of non-volatile memory devices comprise Read Only Memory (ROM), Flash Electrical Erasable Read Only Memory, Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), and Phase Change Memory.
Examples of volatile memory devices comprise Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), however with the disadvantages that, DRAM requires the memory element to be constantly refreshed while SRAM requires a constant supply of energy to maintain the state of the memory element.
Memory cells that employ formation of dendrites, however, are not problem free. Kozicki, et al., U.S. Pat. No. 5,761,115, disclose a PMC memory cell structure (Programmable Metallization Cell) formed from a solid electrolyte located between two electrodes based on the formation of dendrites within the solid electrolyte between two electrodes by raising these electrodes to appropriate potentials. The formation of dendrites provides a means of obtaining a given electrical conduction between two electrodes as soon as a dendritic conducting bridge is set up between the two electrodes. The potentials applied to each of the electrodes can be modified to alter the distribution and number of dendritic conducting bridges to modify electrical conduction between the two electrodes. Inverting the potential between the electrodes breaks the contact of the dendritic conducting bridges between the electrodes by partial dissolution of the bridges and eliminates or reduces electrical conduction.
The PMC cells thus operate in two states: first a so-called “ON” state and secondly a so-called “OFF” state, and act as memory cells. In PMC memory cells, the solid electrolyte may be based on chalcogenides such as GeSe conducting silver ions. This electrolyte is an ionic conductor and electronic insulator, and is usually placed between a silver-based electrode and an inert electrode, for example based on Nickel. No contact is set up in the initial state between the two electrodes that are separated by an insulator. When a bias voltage is applied between the two electrodes, the silver electrode produces Ag+ ions that pass through the electrolyte and are deposited on the opposite electrode, forming one or several metallic silver dendrites. When one or several dendrites pass through the entire thickness of the electrolyte and come into contact with the silver electrode facing them, a conducting bridge is set up and the memory changes to the conducting state. A PMC memory cell can pass very quickly from the conducting state to the insulating state. These two states correspond to memory “write” and “erase” actions.
As noted, PMC memories have disadvantages. After a certain number of write/erase cycles, silver-based dendrites form on the two electrodes facing each other simultaneously. A symmetric silver electrode/electrolyte/silver electrode system forms. This risks creating a path of conducting dendrites between the two electrodes, regardless of the sign of the imposed voltage (positive or negative). But maintaining the erase voltage that should create a break in the dendrite formed on one of the two electrodes, will actually cause formation of a dendrite (on the electrode opposite the first electrode) that will once again short circuit the two electrodes.
Furthermore, the growth of silver dendrites does not take place in a controlled manner. At the end of a certain number of erase/write cycles, the electrolytic medium between the two electrodes is saturated with isolated metallic aggregates, and it becomes impossible to control operation of the system: conducting bridges are set up and dissolved at random during write and erase steps, and the reliability of the device is reduced.
Neuromorphic systems also employ these memory devices. These Neuromorphic systems, also referred to as artificial neural networks, are computational systems that permit electronic systems to essentially function in a manner analogous to that of biological brains. Neuromorphic systems do not generally utilize a traditional digital model of manipulating 0s and 1s. Instead, neuromorphic systems create connections between processing elements that are roughly functionally equivalent to neurons of a biological brain. Neuromorphic systems include various electronic circuits in addition to these memory devices that model biological neurons.
A neuromorphic memory circuit may include a programmable resistive memory element, a conductive axon leaky integrate and fire (LIF) line configured to transmit an axon LIF pulse, and a conductive dendrite LIF line configured to build up a dendrite LIF charge over time. A first transistor is electrically coupled to the dendrite LIF line and the programmable resistive memory element. The first transistor provides a discharge path for the dendrite LIF charge through the programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. A conductive axon spike timing dependent plasticity (STDP) line is configured to transmit an axon STDP pulse. The axon STDP pulse is longer than the axon LIF pulse. A conductive dendrite STDP line is configured to transmit a dendrite STDP pulse after voltage at the dendrite LIF line falls below a threshold voltage. A second transistor is electrically coupled to the axon STDP line and the programmable resistive memory element. The second transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
A neuromorphic memory circuit may also comprise a memory cell array. Each memory cell in the memory cell array includes a programmable resistive memory element, a conductive axon LIF line configured to transmit an axon LIF pulse, and a conductive dendrite LIF line configured to build up a dendrite LIF charge over time. The axon LIF line is electrically coupled to a column of memory cells in the memory cell array. The dendrite LIF line is electrically coupled to a row of memory cells in the memory cell array. A first transistor is electrically coupled to the dendrite LIF line and the programmable resistive memory element. The first transistor provides a discharge path for the dendrite LIF charge through the programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. A conductive axon STDP line is configured to transmit an axon STOP pulse, and a conductive dendrite STDP line is configured to transmit a dendrite STDP pulse after the dendrite LIF charge falls below a threshold voltage. The axon STDP pulse is longer than the axon LIF pulse. Furthermore, the axon STDP line is electrically coupled to the column of memory cells in the memory cell array, and the dendrite STDP line is electrically coupled to the row of memory cells in the memory cell array. A second transistor is electrically coupled to the axon STDP line and the programmable resistive memory element. The second transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
IBM's 2014 TrueNorth neuromorphic CMOS integrated circuit (Merola, et al., Science. 345 (6197): 668. doi:10.1126/science.1254642. PMID 25104385). comprises a manycore processor network on a chip design, with 4096 cores, each one simulating 256 programmable silicon “neurons” for a total of just over a million neurons. In turn, each neuron has 256 programmable “synapses” that convey the signals between them. Hence, the total number of programmable synapses is just over 268 million (http://spectrum.ieee.org/computing/hardware/how-ibm-got-brainlike-efficiency-from-the-truenorth-chip “How IBM Got Brainlike Efficiency From the TrueNorth Chip”)
In terms of basic building blocks, its transistor count is 5.4 billion. Since memory, computation, and communication are handled in each of the 4096 neurosynaptic cores, TrueNorth circumvents the von-Neumann-architecture bottlenecks and is very energy-efficient, consuming 70 milliwatts and a power density that is 1/10,000th of conventional microprocessors. (Cognitive computing: Neurosynaptic chips. IBM. 11 December 201 News Release.). The SyNAPSE chip (introduced mid 2014) operates at lower temperatures and less power because it operates only when it needs, rather than all the time. Higher speed switching devices in these neuromorphic devices, however, would make them even more advantageous. The high speed thin film two terminal chargeable and dischargeable variable resistance battery provides this advantage, along with eliminating dendritic devices from these neuromorphic articles of manufacture, and provides other advantages that will become apparent from the disclosure of the present invention in this specification and the appended drawings.
As to thin film batteries, 3D integration of ail-solid-state rechargeable thin film Li-ion batteries comprise power sources used in many applications such as implantables, sensors and autonomous devices. Niessen, et al., U.S. Patent Application Publication 20100003600 uses these battery stacks as a fully tunable resistor by electrochemical insertion/deinsertion of active species in a host material to change the resistance in this battery stack. Niessen, et al. describe a solid-state variable resistor, comprising a first battery electrode layer deposited on a substrate, a solid electrolyte layer deposited on the first battery electrode layer, a second battery electrode layer deposited on the solid electrolyte layer and two resistor contacts being both in contact with one of the electrode layers. They form the resistor from the electrode material present between the two resistor contacts by creating a path between the contacts and varying the resistance in the path by electrically changing the concentration or the density of the active species in the storage material from which the electrode is formed. This path between the contacts lies in a plane parallel to the planes of two electrodes that sandwich the path.
Niessen, et al., (par. [0050]) however, notes “that changing the resistance in the device [i.e., the Niessen et al. battery] is not as fast as in a MOSFET due to the fact that active species have to be introduced or removed from an active layer by means of electrochemical reactions. This requires a certain amount of time.”
The present invention overcomes some of the foregoing difficulties by providing a high speed electrochemical memory cell device or battery that does not have some of the disadvantages mentioned above, and further provides more sensitive electrochemical memories based on the variation of conductivity of the electrodes.